NEW: Fixed and floating point support packages
This page will provide you with packages tailored to specific EDA software.
VHDL Use model:
For 32 bit, the user would do the following:
library ieee_proposed;
use ieee_proposed.float_pkg.all;
architecture....
signal xxx : float32;
begin
xxx <= yyy + zzz;
Verilog Packages (Documentation)
- fphdl_functions_base.inc - synthesizable number base package
- fphdl16_pkg.v - 16 bit floating point modules
- fphdl16_functions.inc - 16 bit floating point functions
- fphdl32_pkg.v - 32 bit floating point modules
- fphdl32_functions.inc - 32 bit floating point functions
- fphdl64_pkg.v - 64 bit floating point modules
- fphdl64_functions.inc - 64 bit floating point functions
- fphdl_pkg.v - parameterized floating point arithmetic modules
- fphdl_functions.inc - parameterized floating point arithmetic functions
- fphdl64_real_functions_base.inc - 64 bit real number base package
- (VHDL cosimulation models use the VHDL as the base)
- fphdl16_vhdlcos_pkg.v - 16 bit VHDL cosimulation
- fphdl32_vhdlcos_pkg.v - 32 bit VHDL cosimulation
- fphdl64_vhdlcos_pkg.v - 64 bit VHDL cosimulation
- fphdl_vhdlcos_pkg.v - parameterized floating point VHDL cosimulation
Verilog use model
include file, requires parameters definitions, in all parameterized packages
example:
parameter exponent_width = 11; //length of FP exponent
parameter fraction_width = 52; //length of FP fraction
parameter round_style = 0; //rounding option = round_nearest
parameter ieee_extend = 1; //Use IEEE extended FP = true
`include "fphdl_functions.inc"
Some of the more important documents available are:
- The e-mail reflector has been put in "maintenance" mode.
If you wish the reflector to be reactivated, please send me an e-mail.
- Alex Zamfirescu's
Floating point for Synthesis
Links:
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