std_logic_1164_additions.vhdl -- Additions to the package "ieee.std_logic_1164". This package now includes what used to be in "std_logic_textio", so it must be commented out. Otherwise it will
conflict with the new functions (which are much more forgiving).
Usage model:
use ieee.std_logic_1164.all;
-- use ieee.std_logic_textio.all; -- Comment out, included in "_additions".
use ieee_proposed.std_logic_1164_additions.all;
Dependencies: ieee.std_logic_1164;
Note: The contents of the "std_logic_textio" package have now been
included in the "std_logic_1164" package, and an EMPTY "std_logic_textio"
package is provided in the new release.
New funcitons defined in this package:
- Short had aliases:
- to_bv - calls "to_BitVector"
- to_slv - calls "to_StdLogicVector"
- to_sulv - calls "to_stdULogicVector"
- Long hand aliases:
- to_bit_vector - calls "to_BitVector"
- to_std_logic_vector - calls "to_StdLogicVector"
- to_std_ulogic_vector - calls "to_StdULogicVector"
- _reduce functions (and_reduce, nand_reduce, or_reduce ...) are defined
These functions reduce a std_logic_vector (or ulogic) to a single bit.
In vhdl-2008 these will be unary "or", example "or "11011" = '1'"
- "vector" and "std_ulogic" operations are defined. These will perform a
boolean operation of a vector.
Example:
"1" xor "1010" = "0101";
- "\??\" function is defined for "std_ulogic" ("??" operator is release)
if (\??\('1')) then -- will return a "true"
- READ and WRITE procedures for "std_logic_vector", "std_ulogic_vector"
and "std_ulogic" are defined.
- HREAD and HWRITE (Hex read and write) for std_logic_vector
and std_ulogic_vector. These are more "forgiving" than the ones
originally from "std_logic_textio"
- OREAD and OWRITE (octal read and write) for std_logic_vector
and std_ulogic_vector. These are more "forgiving" than the ones
originally from "std_logic_textio"
- BREAD and BWRITE (binary read and write, same as "READ" and "WRITE" for
std_logic_vector and std_ulogic_vector.
- to_string function - Converts a "std_ulogic", "std_logic_vector" or
"std_ulogic_vector" types into a string.
Example:
assert (slv = "101") report "result was " & to_string(slv) severity note;
- to_hstring and to_ostring function (std_(u)logic_vector to hex or octal
string)
Please send feedback to David W. Bishop
dbishop@vhdl.org.