Tckt

class decida.Tckt.Tckt(**kwargs)

Bases: decida.ItclObjectx.ItclObjectx

procedural simulation test-circuit class.

synopsis:

constructor arguments:

**kwargs (dict)

keyword=value specifications:

configuration-options

configuration options:

verbose (bool, default=False)

Enable/disable verbose mode.

project (str, default="")

Specify project name. The project must be one of the supported projects (one of the Tckt._ProjectDB entries)

simulator (str, default="spectre")

Specify the circuit simulator. Must be one of:

  • hspice : Synopsys HSpice
  • sspice : Silvaco SmartSpice
  • ngspice : UC Berkeley NGspice
  • spectre : Cadence Spectre
simulator_args (str, default="")

string of additional simulator command-line arguments

case (str, default="case")

specify the process/supply voltage/temperature case corner, by its name. Must be one of the cases specified for the current project, and one of the supported cases (specified in Tckt._CaseDB)

path (list of str, default=["."])

list of paths to search for the circuit netlist.

netlistfile (str, default="")

name of the netlist file

prefix (str, default="")

prefix to generated files. Should be a unique name for each simulation.

title (str, default="")

title to be added to top of generated input file.

testdir (str, default="")

directory where tests are performed. (Not currently used).

resultsdir (str, default="")

directory where simulation results are written. If resultsdir is not specified, results are written to the current directory.

circuit (str, default="")

the name of the device under test. This is a convenience name for documenting generated files.

temp_nom (float, default=25.0)

nominal simulation temperature.

temp_low (float, default=_40.0)

low simulation temperature.

temp_high (float, default=150.0)

high simulation temperature.

supply_nom (float, default=1.0)

nominal supply voltage value.

supply_low (float, default=0.9)

low supply voltage value.

supply_high (float, default=1.1)

high supply voltage value.

example:

public methods:

  • public methods from ItclObjectx
bin2thm(binval, nbits)

generate thermometer value from binary value.

arguments:

binval (int)

binary value

nbits

number of bits in thermometer value

results:

  • returns thermometer code string : nbits’b1111...
ckey2case(ckey)

get case corner name from case key.

arguments:

ckey (str)

case integer index (key)

results:

  • returns a PVT case corner name corresponding to the case key.
control(s)

specify simulation control string.

arguments:

s (str)

a string to be inserted in the input file directly. This is in the same language of the simulator itself.

results:

  • python variables are interpolated into the control section
  • the control section is included at the end of the simulator input file.
dcop(rawfile=None, lisfile=None, idmin=1e-08, vdssmin=0.01, verbose=False, block=0)

view results from DC operating point analysis.

arguments:

idmin (float, default=1e_8)

The minimum drain current to consider a device as being on.

vdssmin (float, default=0.01)

The minimum difference between the drain voltage and the saturation voltage to consider a device as being saturated.

verbose (bool, default=False)

If True, print verbose messages.

block (int, default=0)

Specify the block to process in the data file.

elements(s)

collect element value replacement specifications.

arguments:

s (str)

each (newline-separated) line of s is a specification of a value for the sources in the netlist.

example element definitions:

  • vin sin 0.6 0.2 $freq

    replace the value of the voltage source with a sine spec.

  • vbg netlist

    use the existing vbg value in the netlist. This marks the source as recognized and no warning message is printed for the source not being specified.

  • vdd $vdd

    use the value of the python-script variable vdd

  • vsd<3:0> 5’b0011 v0=0.0 v1=$vdd

    specify a bus of values. The digital 0 value is 0.0V and the digital 1 value is vdd V.

  • vdac_in<9:0> counter v0=0.0 v1=$vdd edge=$edge hold=$hold

    specify that vdac_in counts up from 0 to the maximum value with rise-time = edge and hold-time = hold.

generate_inputfile()

write simulator input file based on netlist, control, monitor specs.

results:

  • calls spice or spectre input file generator.
generate_spectre_inputfile()

write (spectre) simulator input file based on netlist, control, monitor specs.

results:

  • generates input file for spectre.
  • starting with the netlist file, specified element values are inserted, output voltages and currents are specified, and the control section is included.
generate_spice_inputfile()

write (spice) simulator input file based on netlist, control, monitor specs.

results:

  • generates input file for spice.
  • starting with the netlist file, specified element values are inserted, output voltages and currents are specified, and the control section is included.
get_case_key()

get key of current process, voltage, temperature (case) corner.

results:

  • get the integer index (key) of the current case corner.
get_datafile(analysis='tr')

get simulator waveform data file.

arguments:

analysis (str, default="tr")

used for HSpice which names the output file with the simulation analysis.

results:

  • get the simulator waveform data file path.
get_inputfile()

get simulator input file.

results:

  • get the input file path.
get_modelfile()

get modelfile.

results:

  • get the modelfile of the current project.
get_outputfile()

get simulator output file.

results:

  • get the output file path.
get_process()

get process corner.

results:

  • get the process name (model file library) for the current PVT case corner.
get_tech()

get technology.

results:

  • get name of the current technology name.
get_temp()

get temperature.

results:

  • get the temperature for the current PVT case corner.
get_test()

get name of calling routine.

results:

  • get name of the routine from the calling frame.
get_vdd()

get power-supply voltage.

results:

  • get the power-supply voltage for the current PVT case corner.
get_xnmos()

get nmos subcircuit device.

results:

  • get the NMOS device path in the NMOS subcircuit model for the current project.
get_xpmos()

get pmos subcircuit device.

results:

  • get the PMOS device path in the PMOS subcircuit model for the current project.
is_already_done()

return true if data file already exists.

results:

  • return True if the data file is already present. Can be used to re-perform an uncompleted loop of conditions, and skip the ones already performed.
modeldir = '/Users/richard/.DeCiDa/models/'
monitor(string)

collect monitor specifications.

arguments:

string (str)

a string of space-separated monitor items.

example monitor items:

  • REF : monitor voltage of node REF
  • VCD<3:0> : monitor voltage of nodes VCD_3, ... , VCD_0
  • I(vsc) : monitor current in voltage source vsc
  • IDN(mn1) : monitor drain current in mosfet xmn1
  • IR(res) : monitor current in resistor res
  • IX(xa1.p) : monitor current in subcircuit xa1, node p
  • PN(mn1-vdsat) : monitor mosfet xmn1 vdsat parameter
  • @Xgmc: : following specs are for subcircuit Xgmc
  • @Xgmc.Xq: : following specs are for subcircuit Xgmc.Xq
  • @: : following specs are for top-level circuit
netlist_remove(s)

specify subcircuits or instances to remove from the netlist

arguments:

s (str)

a subcircuit name or instance name to remove from the netlist.

no_data()

return true if data file doesn’t exist.

results:

  • return True if there is no data file. Can be used in a script report section to skip over loop-conditions which haven’t been done yet.
number_of_data_blocks()

return number of blocks in the simulated data file.

results:

  • count the number of lines begining with “Plotname” in a nutmeg-format data file.
postlayout(inst, subckt, file)

collect postlayout specifications.

arguments:

inst (str)

full path of instance in testbench schematic to replace with postlayout representation. used to modify monitor specs.

subckt (str)

specifies subcircuit to replace. Tckt.netlist_remove() is used to remove the subcircuit.

file (str)

specifies path to postlayout netlist. used to generate .include file.

static project_cases(project)

return PVT case corners of project in the database.

static project_modelfile(project)

return modelfile of project in the database.

static project_tech(project)

return technology of project in the database.

static projects()

return valid projects in the database.

simulate(simulate=True, clean=False, remote='')

perform simulation.

arguments:

simulate (bool, default=True)

if True, proceed to simulate. Otherwise simply print the simulation command.

clean (bool, default=False)

if True, remove the input file and output file, leaving only the data file.

remote (str, default="")

if specified, generate a command deck and submit as a batch job on the named remote host.

static spectre_dcop_mosfet_id_sort(mosfet1, mosfet2)

sort two mosfets according to drain current.

stability_analysis(plot=True, save=True)

perform stability analysis.

arguments:

plot (bool, default=True)

If True, plot loop-gain and loop-phase after simulation.

save (bool, default=True)

If True, save the collated loop simulation results.

test_select(tests, selected_tests=None)

display dialog for selecting tests, or directly select tests.

arguments:

tests (list of str)

list of available tests in the script.

selected_tests (list of str, default=None)

list of tests which are supplied directly.

results:

  • if selected_tests is not None, return a list of these tests in the same order that they appear in the tests argument.
  • if selected_tests is None, display a dialog to select the tests.
veriloga(subckt, file, parameters='')

collect verilog-A specifications.

arguments:

subckt (str)

subcircuit name to use verilog-A representation.

file (str)

verilog-A module file.

parameters (str, default="")

string of space-separated parameter-name=value entries.

wait_for_data(interval=5)

wait until datafile appears and is non-zero.

arguments:

interval (int, default=5)

seconds to wait before re-checking for the existence of the data file.

results:

  • the script waits until the data file has been produced and is not empty.

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