NetworkSim.system_verilog.receiver
.generate_testvector¶
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NetworkSim.system_verilog.receiver.
generate_testvector
(simulator, receiver_id=1, id_width=7, address_width=8, data_width=128, output_dir=None)[source]¶ Generate testvector files for receiver module.
The underlying clock cycle is 1 ns and testvectors are generated for every clock cycle. The end time is the until value of the simulator.
- Parameters
simulator (BaseSimulator) – The simulator used for the simulation.
receiver_id (int, optional) – The ID of the receiver of interest, by default 1.
address_width (int, optional) – The bit width of the receiver RAM address, by default 8.
data_width (int, optional) – The bit width of data signal, by default 128.
output_dir (str, optional) – Output directory for the testvectors, by default None (the testvectors directory under Digital-Design).
- Returns
data_in, ram_assert – Two lists containing input data signal and RAM content to be checked against.
- Return type
list